190 lines
6.3 KiB
Diff
190 lines
6.3 KiB
Diff
From: Josh Lay <me@jlay.io>
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Date: Fri, 12 Oct 2018 11:17:23 -0600
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Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.18)
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This an updated version of Alex Williamson's patch from:
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https://lkml.org/lkml/2013/5/30/513
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To build on Fedora 28 kernels 4.18.x
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Original commit message follows:
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---
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PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that
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allows us to control whether transactions are allowed to be redirected
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in various subnodes of a PCIe topology. For instance, if two
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endpoints are below a root port or downsteam switch port, the
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downstream port may optionally redirect transactions between the
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devices, bypassing upstream devices. The same can happen internally
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on multifunction devices. The transaction may never be visible to the
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upstream devices.
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One upstream device that we particularly care about is the IOMMU. If
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a redirection occurs in the topology below the IOMMU, then the IOMMU
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cannot provide isolation between devices. This is why the PCIe spec
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encourages topologies to include ACS support. Without it, we have to
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assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation.
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Unfortunately, far too many topologies do not support ACS to make this
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a steadfast requirement. Even the latest chipsets from Intel are only
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sporadically supporting ACS. We have trouble getting interconnect
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vendors to include the PCIe spec required PCIe capability, let alone
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suggested features.
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Therefore, we need to add some flexibility. The pcie_acs_override=
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boot option lets users opt-in specific devices or sets of devices to
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assume ACS support. The "downstream" option assumes full ACS support
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on root ports and downstream switch ports. The "multifunction"
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option assumes the subset of ACS features available on multifunction
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endpoints and upstream switch ports are supported. The "id:nnnn:nnnn"
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option enables ACS support on devices matching the provided vendor
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and device IDs, allowing more strategic ACS overrides. These options
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may be combined in any order. A maximum of 16 id specific overrides
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are available. It's suggested to use the most limited set of options
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necessary to avoid completely disabling ACS across the topology.
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Note to hardware vendors, we have facilities to permanently quirk
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specific devices which enforce isolation but not provide an ACS
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capability. Please contact me to have your devices added and save
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your customers the hassle of this boot option.
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Signed-off-by: Mark Weiman <mark.weiman@markzz.com>
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---
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diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
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index efc7aa7a0670..b5258db83441 100644
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--- a/Documentation/admin-guide/kernel-parameters.txt
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+++ b/Documentation/admin-guide/kernel-parameters.txt
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@@ -3028,6 +3028,15 @@
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nomsi [MSI] If the PCI_MSI kernel config parameter is
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enabled, this kernel boot option can be used to
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disable the use of MSI interrupts system-wide.
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+ pcie_acs_override =
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+ [PCIE] Override missing PCIe ACS support for:
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+ downstream
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+ All downstream ports - full ACS capabilities
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+ multfunction
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+ All multifunction devices - multifunction ACS subset
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+ id:nnnn:nnnn
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+ Specfic device - full ACS capabilities
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+ Specified as vid:did (vendor/device ID) in hex
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noioapicquirk [APIC] Disable all boot interrupt quirks.
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Safety option to keep boot IRQs enabled. This
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should never be necessary.
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diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
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index f439de848658..6431f60a56f4 100644
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -3353,6 +3353,106 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
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dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
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}
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+static bool acs_on_downstream;
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+static bool acs_on_multifunction;
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+
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+#define NUM_ACS_IDS 16
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+struct acs_on_id {
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+ unsigned short vendor;
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+ unsigned short device;
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+};
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+static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
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+static u8 max_acs_id;
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+
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+static __init int pcie_acs_override_setup(char *p)
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+{
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+ if (!p)
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+ return -EINVAL;
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+
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+ while (*p) {
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+ if (!strncmp(p, "downstream", 10))
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+ acs_on_downstream = true;
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+ if (!strncmp(p, "multifunction", 13))
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+ acs_on_multifunction = true;
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+ if (!strncmp(p, "id:", 3)) {
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+ char opt[5];
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+ int ret;
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+ long val;
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+
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+ if (max_acs_id >= NUM_ACS_IDS - 1) {
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+ pr_warn("Out of PCIe ACS override slots (%d)\n",
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+ NUM_ACS_IDS);
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+ goto next;
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+ }
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+
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+ p += 3;
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+ snprintf(opt, 5, "%s", p);
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+ ret = kstrtol(opt, 16, &val);
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+ if (ret) {
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+ pr_warn("PCIe ACS ID parse error %d\n", ret);
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+ goto next;
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+ }
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+ acs_on_ids[max_acs_id].vendor = val;
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+
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+ p += strcspn(p, ":");
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+ if (*p != ':') {
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+ pr_warn("PCIe ACS invalid ID\n");
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+ goto next;
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+ }
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+
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+ p++;
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+ snprintf(opt, 5, "%s", p);
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+ ret = kstrtol(opt, 16, &val);
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+ if (ret) {
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+ pr_warn("PCIe ACS ID parse error %d\n", ret);
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+ goto next;
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+ }
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+ acs_on_ids[max_acs_id].device = val;
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+ max_acs_id++;
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+ }
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+next:
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+ p += strcspn(p, ",");
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+ if (*p == ',')
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+ p++;
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+ }
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+
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+ if (acs_on_downstream || acs_on_multifunction || max_acs_id)
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+ pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
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+
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+ return 0;
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+}
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+early_param("pcie_acs_override", pcie_acs_override_setup);
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+
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+static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
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+{
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+ int i;
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+
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+ /* Never override ACS for legacy devices or devices with ACS caps */
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+ if (!pci_is_pcie(dev) ||
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+ pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
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+ return -ENOTTY;
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+
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+ for (i = 0; i < max_acs_id; i++)
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+ if (acs_on_ids[i].vendor == dev->vendor &&
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+ acs_on_ids[i].device == dev->device)
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+ return 1;
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+
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+ switch (pci_pcie_type(dev)) {
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+ case PCI_EXP_TYPE_DOWNSTREAM:
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+ case PCI_EXP_TYPE_ROOT_PORT:
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+ if (acs_on_downstream)
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+ return 1;
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+ break;
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+ case PCI_EXP_TYPE_ENDPOINT:
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+ case PCI_EXP_TYPE_UPSTREAM:
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+ case PCI_EXP_TYPE_LEG_END:
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+ case PCI_EXP_TYPE_RC_END:
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+ if (acs_on_multifunction && dev->multifunction)
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+ return 1;
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+ }
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+
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+ return -ENOTTY;
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+}
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/*
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* Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
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* The device will throw a Link Down error on AER-capable systems and
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@@ -4395,6 +4495,7 @@ static const struct pci_dev_acs_enabled {
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{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
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{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
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{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
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+ { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
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{ 0 }
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};
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